What Are Assembly Assessment Wafers?
Assembly assessment wafers carry TEG (Test Element Group) patterns for assessing semiconductor packaging materials and bonding processes. A TEG is a test pattern used to assess materials, processes, and electrical connections.
Philtech can assess the feasibility of fabricating assembly assessment wafers, including interconnect patterns and connection specifications, based on the assessment objectives and customer requirements.
Main Applications
Contact us to discuss fabrication of assembly assessment wafers.
Contact UsAn example of an assembly assessment wafer fabricated by Philtech is shown below.
Daisy-Chain TEG (PT035)
PT035 is a daisy-chain TEG fabricated by Philtech for assembly assessment. Bonding PT035A and PT035B, which have different interconnect patterns, forms a daisy chain with multiple connections linked in series. Continuity and changes in resistance indicate the condition of the complete connection path.
Cross-Sectional Structure
Common Specifications
| Item | Specification |
|---|---|
| Pad pitch | 40 µm |
| Pad size | 20 µm |
| Interconnect width | 16um |
| Passivation opening size | 7 µm |
| UBM size | 15 µm |
PT035A / PT035B Layouts
The interconnects on PT035A and PT035B are aligned so that the return paths connect through the bumps, forming a daisy chain in series.
PT035A (8 mm × 8 mm)
PT035B (6 mm × 6 mm)
*The wafer also contains current-branching test chips with different bump counts, in addition to those shown above.
SEM Images After Bump Formation
The SEM (scanning electron microscope) images show the bumps after formation: nickel/gold (NiAu) bumps on PT035A on the left, and tin/silver (SnAg) bumps on PT035B on the right.
TSV Interposer
A TSV (Through Silicon Via) filled with a conductive metal such as Cu forms an electrical interconnect through a silicon substrate.
Philtech has experience fabricating TSV interconnects through silicon substrates.
