Assembly Evaluation Wafers
Assembly evaluation wafers carry TEG (Test Element Group) patterns for evaluating semiconductor packaging materials and bonding processes. TEG refers to evaluation patterns used to check materials, processes, and the condition of electrical connections.
Philtech can discuss fabrication of assembly evaluation wafers, including interconnect patterns and connection specifications, based on the intended evaluation and your requirements.
Main Applications
Discuss Fabrication of Assembly Evaluation Wafers
Contact UsFabrication Example | Daisy-Chain TEG (PT035)
PT035 is a daisy-chain TEG fabricated by Philtech, consisting of PT035A and PT035B test chips with different interconnect patterns. When the two interconnect patterns are aligned and their loopback traces are joined through bump connections, multiple connections form a series path. The condition of the entire connection path can be checked by testing for continuity and changes in resistance.
Cross-Sectional Structure Example
Common Specifications for PT035A / PT035B
| Item | Details |
|---|---|
| Pad pitch | 40 µm |
| Pad size | 20 µm |
| Interconnect width | 16 µm |
| Passivation opening size | 7 µm |
| UBM size | 15 µm |
PT035A / PT035B Layouts
PT035A (8 mm × 8 mm)
PT035B (6 mm × 6 mm)
Note: In addition to the chips shown above, the wafer also includes shunt chips with different bump counts.
SEM Observation After Bump Formation
Fabrication Example | TSV Interposer
Through-silicon electrodes are interconnects that pass through a silicon substrate, formed by filling TSVs (Through Silicon Vias) with conductive metals such as Cu.
The image below is a cross-sectional SEM of an example interposer in which Philtech formed TSV electrodes.
