Hole Pattern Wafers

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Hole Patterned Wafers

It is mainly used to evaluate the coverage of film deposition equipment(CVD,ALD,PVD etc.) and materials.

1. 0.14um Hole Patterned Wafer

Φ0.14um hole pattern formed on 500nm plasma CVD SiO film. It is mainly used to evaluate the coverage of film deposition equipment such as sputtering, CVD, and ALD. The SEM photo on the right is an example of coverage evaluation of Cu sputtering.

Cu Sputter Coverage Evaluation　Hole Diameter : 0.14um

2. 20um Hole　Cu ECP Evaluations

Without Void

With Void

This is a hole pattern processed directly on a silicon substrate.
Used to evaluate the embedding characteristics of Cu plating for TSV electrodes.
By changing the Cu plating conditions, the occurrence of voids inside the hole will change.
Please inquire about your desired hole diameter and hole depth.