Charging Damage Monitor Wafers & Chips

Evaluation Applications and What They Reveal

Equipment and Process Evaluation

These monitors are used to evaluate equipment and processes where charging is a concern, including etching, ashing, CVD, PVD, ion implantation, atmospheric-pressure plasma, and drying after cleaning. Comparing I‑V curves reveals differences when equipment or conditions change and trends before and after improvements.

Potential evaluation applications include:

• Checking charging damage during the development of new semiconductor manufacturing equipment
• Checking equipment condition after installation, startup, modification, or maintenance
• Comparing conditions when process parameters or recipes change
• Comparing trends across equipment or chambers
• Identifying locations where damage is concentrated across the wafer and isolating the causes
• Periodically monitoring manufacturing processes and checking for deviations from normal conditions
• Investigating process and yield improvements to limit degradation of oxide reliability

Examining the Distribution Across the Wafer

The gate-oxide breakdown voltage from each I‑V curve is color-coded and shown on a wafer map. The colors and voltage values reveal differences between the wafer center and edge, as well as trends concentrated in specific regions.

Examining Sensitivity by Antenna Ratio

Standard measurements use 4 antenna ratios—2.5K, 10K, 100K, and 1M—to examine differences in sensitivity to charging damage. Patterns with larger antenna ratios collect charge over a larger antenna area for the same gate area, making them suitable for evaluation at higher sensitivity.

Evaluation Principles and Monitor Structure

Charge generated during plasma processing and other processes collects on the antenna and is injected into the gate oxide of the MOS capacitor. In these antenna MOS test structures, known as a TEG (test element group), current flowing through the oxide increases defects in the film. When accumulated damage exceeds a threshold, leakage current rises sharply, leading to dielectric breakdown.

In the 300 mm wafer type shown here, LOCOS provides device isolation, and a phosphorus-doped Poly-Si electrode and thermal oxide form the MOS capacitor. The cross-sectional structure consists of a 320 nm thermally grown field oxide, a 4 nm gate oxide, and a 460 nm doped Poly-Si electrode.

Chip Layouts and Patterns with Different Antenna Ratios

Chip Layouts

BOX antennas for charging evaluation are arranged within each chip.

Chip Layout for 300 mm Wafers

Chip Layout for 200 mm Wafers

Antenna-Ratio Patterns

Patterns with different antenna ratios are included on the same chip.

Measurement Method: Creating I‑V Curves and Breakdown-Voltage Maps

1. 01

   Load the Sample

   Place the wafer or chip on the probe station after plasma processing.
2. 02

   Connect the Electrodes

   Connect the Poly-Si gate electrode pad as the negative electrode and the backside Si as the positive electrode.
3. 03

   Acquire I‑V Characteristics

   Measure the current while increasing the applied voltage in steps.
4. 04

   Compile the Results in Excel

   Include the I‑V curves and a breakdown-voltage map color-coded by measurement location.

Breakdown voltage is defined as the voltage at which the current through the 4 µm² active area exceeds 1 µA. A breakdown-voltage map shows the results at each measured chip location. In standard measurements of 300 mm wafers, about 25% of the valid chips are typically selected in a checkerboard pattern for measurement.

Evaluation Examples and Measurement Locations

300 mm: Initial Measurement Results and 2 Process Evaluation Examples

Initial measurement results and results after plasma processing are shown for antenna ratios of 2.5K, 10K, 100K, and 1M. The post-process evaluation examples compare differences in I‑V curves and use breakdown-voltage maps to examine trends across the wafer at each measurement location.

Initial Measurement Results

Evaluation Example 1

Evaluation Example 2

Measurement Locations for 200 mm Wafers

Image key: cyan cells indicate measured chips.

From Ordering to Delivery of Measurement Data in Excel: Workflow and Typical Lead Times

1. 01

   Confirm Specifications

   Confirm the wafer diameter, wafer or chip format, and process to be evaluated.
   
2. 02

   Shipment

   We ship the wafers or chips. The typical lead time to ship in-stock items is about 1 week.
   
3. 03

   Plasma Processing

   The customer performs plasma processing.
   
4. 04

   Sample Return

   The customer returns the processed wafers or chips.
   
5. 05

   I‑V Measurement

   We measure the I‑V curves of the returned samples and evaluate them primarily on the basis of these results.
   
6. 06

   Results Delivery

   We provide I‑V curves and breakdown-voltage maps in Excel, typically about 2 weeks after receipt of the samples.
   

Shipping lead times and measurement times vary with stock availability, specifications, and scheduling. These estimates exclude customer processing time and transit time, so the overall turnaround time is provided individually.